1. Technical Field
The present invention relates generally to integrated circuit power supply distribution, and more particularly, to a methodology and substrate that has reduced power supply resistance from external power supply terminals to the die power supply connections.
2. Description of the Related Art
High-density interconnect schemes for processor packages, as well as other very-large-scale integrated (VLSI) circuits, typically use a large number of circuit layers to connect one or more dies to electrical terminals disposed on one or more surfaces of the package, as well as to interconnect multiple dies in multi-die packages. Power distribution in packages having bottom-side terminals and top side die mounting is typically performed by including multiple v cias connecting power supply terminals of the one or more dies to power supply planes that are disposed at metal layers at or near the bottom of the substrate. In packages having no power supply planes, power supply distribution is generally accomplished using vias extending from the die power supply terminals to the package terminals.
When distributing power to dies such as those including one or more processors, a very low resistance path from the power supply terminals to the die is a requirement. Present-day VLSI integrated circuits such as processors, can require power supply currents in excess of 100 amperes and operate at power supply voltages of less than one volt. A net power supply path resistance of 0.005 milliohms will result in a power dissipation of 50 Watts under such conditions, which is 50% of the total power consumption. The resulting drop in voltage would require a 2 volt power supply to deliver 1 volt at the die.
Therefore, large numbers of commonly-connected die terminals, vias and package terminals are included for each power supply connection (including return paths such as ground), to ensure that the overall resistance of each power supply path does not result in substantial power loss and voltage drop. The vias are typically placed under the die and/or near the edges of the die, to reduce the power supply path resistance.
However, such power supply distribution consumes routing resources that could otherwise be utilized for routing signal paths, thereby increasing the size, weight, cost and complexity of the substrate and package. Further, inclusion of power supply vias near or under the die to decrease path resistance either requires placement of decoupling capacitors adjacent to the die, or placement of wide conductors extending to the decoupling capacitors further away from die, limiting critical signal routing resources near the edges of the die. Resources are further limited since manufacturing processes limit the number of layers a via can transit before requiring a “jog” or lateral displacement. The vias for power supplies are numerous and/or larger that signal vias in order to decrease resistance, and therefore the requirement to place power supply vias under or near the die drastically reduces the signal routing resources that would otherwise be available.
Therefore, it is desirable to provide a substrate for an integrated circuit package, and a method for making a substrate for an integrated circuit package, that frees up routing resources in the vicinity of the die(s) by routing power supply connections from the die(s) to external terminals in regions away from the die(s).